A Framework for Fault Tolerance in RISC-V

Microcontrollers require protection against transient and permanent faults when being utilized for safety-critical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy. This work incorporates fault tolerance techniques of those domains into a framework for RISC-V processors. The implemented fault tolerance components are highly configurable to satisfy various dependability requirements. The cost of applied fault tolerance mechanisms is evaluated for both an FPGA and an ASIC implementation. Fault injection tests prove the effectiveness for error detection and cover both transient and permanent faults in logic and memories. New methods are introduced to minimize the error detection latency and achieve a reduction of up to 79%.


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