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A comparative survey of open-source application-class RISC-V processor implementations

Affiliation/Institute
Institute of Computer and Network Engineering (IDA), Technische Universität Braunschweig
Dörflinger, Alexander;
Affiliation/Institute
Institute of Computer and Network Engineering (IDA), Technische Universität Braunschweig
Albers, Mark;
Affiliation/Institute
Institute of Computer and Network Engineering (IDA), Technische Universität Braunschweig
Kleinbeck, Benedikt;
Affiliation/Institute
Institute of Computer and Network Engineering (IDA), Technische Universität Braunschweig
Guan, Yejun;
Affiliation/Institute
Institute of Computer and Network Engineering (IDA), Technische Universität Braunschweig
Michalik, Harald;
Affiliation/Institute
Institute of Computer Engineering (ITI), Universität zu Lübeck
Klink, Raphael;
Affiliation/Institute
Institute of Computer Engineering (ITI), Universität zu Lübeck
Blochwitz, Christopher;
Affiliation/Institute
Institute of Computer Engineering (ITI), Universität zu Lübeck
Nechi, Anouar;
Affiliation/Institute
Institute of Computer Engineering (ITI), Universität zu Lübeck
Berekovic, Mladen

The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology.

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License Holder: © ACM, 2021. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in https://dl.acm.org/doi/10.1145/3457388.3458657

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